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1 for more information www.linear.com/lt3581 typical application description 3.3a boost/inverting dc/dc converter with fault protection the lt ? 3581 is a pwm dc/dc converter with built-in fault protection features to aid in protecting against output shorts, input/output overvoltages, and overtemperature conditions. the part consists of a 42v master switch, and a 42v slave switch that can be tied together for a total current limit of 3.3a. the lt3581 is ideal for many local power supply designs. it can be easily configured in boost, sepic, inverting or flyback configurations, and is capable of generating 12v at 830ma, or C12v at 625ma from a 5v input. in addition, the lt3581s slave switch allows the part to be configured in high voltage, high power charge pump topologies that are very efficient and require fewer components than traditional circuits. the lt3581s switching frequency range can be set bet ween 200khz and 2.5mhz. the part may be clocked internally at a frequency set by the resistor from the r t pin to ground, or it may be synchronized to an external clock. a buffered version of the clock signal is driven out of the clkout pin, and may be used to synchronize other compatible switching regulator ics to the lt3581. the lt3581 also features innovative shdn pin circuitry that allows for slowly varying input signals and an adjustable undervoltage lockout function. additional features such as frequency foldback and soft-start are integrated. the lt3581 is available in 14-pin 4mm 3mm dfn and 16- lead mse packages. output short protected, 5v to 12v boost converter operating at 2mhz features applications n 3.3a, 42v combined power switch n master/slave (1.9a/1.4a) switch design n output short circuit protection n wide input range: 2.5v to 22v operating, 40v maximum transient n switching frequency up to 2.5mhz n easily configurable as a boost, sepic, inverting or flyback converter n user configurable undervoltage lockout n low v cesat switch: 250mv at 2.75a (typical) n can be synchronized to external clock n can be synchronized to other switching regulators n high gain shdn pin accepts slowly varying input signals n 14-pin 4mm 3mm dfn and 16-lead mse packages n local power supply n vacuum fluorescent display (vfd) bias supplies n tft-lcd bias supplies n automotive engine control unit (ecu) power l , lt, ltc, ltm, linear technology and the linear logo are registered trademarks of linear technology corporation. all other trademarks are the property of their respective owners. protected by u.s. patents, including 7579816. v in 5v v in 6.04k 100k 130k 43.2k 4.7f 1.5h 1nf 3581 ta01 0.1f 4.7f 10.5k 4.7f v out 12v 830ma sw1 sw2 fb clkout gate v c ss v in rt gnd sync fault shdn lt3581 56pf 18.7k 10k load current (ma) 0 50 efficiency (%) power loss (mw) 55 65 70 75 400 100 95 3581 ta01b 60 200 1000 800 600 80 85 90 0 200 600 2000 1200 1400 1600 1800 400 800 1000 efficiency and power loss vs load current lt3581 3581fb
2 for more information www.linear.com/lt3581 pin configuration absolute maximum ratings v in voltage ................................................. C 0.3v to 40v sw1/sw2 voltage ..................................... C0 .4v to 42v rt voltage ................................................... C 0.3v to 5v ss, fb voltage .......................................... C 0.3v to 2.5v v c voltage .................................................... C 0.3v to 2v shdn voltage ............................................ C 0.3v to 40v sync voltage ............................................ C 0.3v to 5.5v gate voltage ............................................. C 0.3v to 80v fa u lt voltage ............................................ C 0.3v to 40v (note 1) 1 2 3 4 5 6 7 14 13 12 11 10 9 8 sync ss rt shdn clkout sw2 sw2 fb v c gate fault v in sw1 sw1 top view de14 package 14-pin (4mm 3mm) plastic dfn 15 gnd t jmax = 125c, ja = 43c/w, jc = 4.3c/w exposed pad (pin 15) is gnd, must be soldered to pcb 1 2 3 4 5 6 7 8 fb v c gate fault v in sw1 sw1 sw1 16 15 14 13 12 11 10 9 sync ss rt shdn clkout sw2 sw2 sw2 top view mse package 16-lead plastic msop 17 gnd t jmax = 125c, ja = 45c/w, jc = 10c/w exposed pad (pin 17) is gnd, must be soldered to pcb order information lead free finish tape and reel part marking* package description temperature range lt3581ede#pbf lt3581ede#trpbf 3581 14-lead (4mm 3mm) plastic dfn C40c to 125c lt3581ide#pbf lt3581ide#trpbf 3581 14-lead (4mm 3mm) plastic dfn C40c to 125c lt3581hde#pbf lt3581hde#trpbf 3581 14-lead (4mm 3mm) plastic dfn C40c to 150c lt3581emse#pbf lt3581emse#trpbf 3581 16-lead plastic msop C40c to 125c lt3581imse#pbf lt3581imse#trpbf 3581 16-lead plastic msop C40c to 125c consult ltc marketing for parts specified with wider operating temperature ranges. *the temperature grade is identified by a label on the shipping container. consult ltc marketing for information on non-standard lead based finish parts. for more information on lead free part marking, go to: http://www.linear.com/leadfree/ for more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/ fa u lt current ..................................................... 500a clkout voltage .......................................... C 0.3v to 3v clkout current ....................................................... 1ma operating junction temperature range lt3581e (notes 2, 4) ......................... C4 0c to 125c lt3581i (notes 2, 4) .......................... C4 0c to 125c lt 3581h (notes 2, 4) ......................... C 40c to 150c storage temperature range .................. C 65c to 150c lt3581 3581fb
3 for more information www.linear.com/lt3581 electrical characteristics parameter conditions min typ max units minimum input voltage l 2.3 2.5 v v in overvoltage lockout 22.1 23.5 25 v positive feedback voltage l 1.195 1.215 1.230 v negative feedback voltage l 3 9 16 mv positive fb pin bias current v fb = positive feedback voltage, current into pin l 81 83.3 85 a negative fb pin bias current v fb = negative feedback voltage, current out of pin l 81 83.3 85.5 a error amp transconductance i = 10a 270 mhos error amp voltage gain 70 v/v quiescent current not switching 1.9 2.3 ma quiescent current in shutdown v shdn = 0v 0 1 a reference line regulation 2.5v v in 20v 0.01 0.05 %/v switching frequency, f osc r t = 34k l 2.25 2.5 2.75 mhz r t = 432k l 180 200 220 khz switching frequency in foldback compared to normal f osc 1/6 ratio switching frequency range free-running or synchronizing l 200 2500 khz sync high level for synchronization l 1.3 v sync low level for synchronization l 0.4 v sync clock pulse duty cycle v sync = 0v to 2v 20 80 % recommended minimum sync ratio f sync /f osc 3/4 minimum off-time 45 ns minimum on-time 55 ns sw1 current limit at all duty cycles l 1.9 2.4 3 a current sharing (sw2/sw1) 78 % sw1 + sw2 current limit at all duty cycles, sw2/sw1 = 78% (note 3) l 3.3 4.3 5.4 a switch v cesat sw1 & sw2 tied together, i sw1 + i sw2 = 2.75a 250 mv sw1 leakage current v sw1 = 5v 0.01 1 a sw2 leakage current v sw2 = 5v 0.01 1 a the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c. v in = 5v, v shdn = v in , v fault = v in , unless otherwise noted. (note 2). lt3581 3581fb
4 for more information www.linear.com/lt3581 note 1: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. exposure to any absolute maximum rating condition for extended periods may affect device reliability and lifetime. note 2: the lt3581e is guaranteed to meet performance specifications from 0c to 125c. specifications over the C40c to 125c junction temperature range are assured by design, characterization and correlation with statistical process controls. the lt3581i is guaranteed over the full C40c to 125c operating junction temperature range. the lt3581h is electrical characteristics the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c. v in = 5v, v shdn = v in , v fault = v in , unless otherwise noted. (note 2). parameter conditions min typ max units soft-start charge current v ss = 30mv, current flows out of ss pin l 5.7 8.7 11.3 a soft-start discharge current part in fault, v ss = 2.1v, current flows into ss pin l 5.7 8.7 11.3 a soft-start high detection voltage part in fault l 1.65 1.8 1.95 v soft-start low detection voltage part exiting fault l 30 50 85 mv shdn minimum input voltage high active mode, shdn rising (lt3581e, lt3581i) active mode, shdn rising (lt3581h) active mode, shdn falling (lt3581e, lt3581i, lt3581h) l l l 1.27 1.27 1.24 1.33 1.33 1.3 1.41 1.44 1.38 v v v shdn input voltage low shutdown mode l 0.3 v shdn pin bias current v shdn = 3v v shdn = 1.3v v shdn = 0v 9.7 40 11.4 0 60 13.4 0.1 a a a clkout output voltage high c clkout = 50pf 1.9 2.1 2.3 v clkout output voltage low c clkout = 50pf 5 200 mv clkout duty cycle t j = 25c 42 % clkout rise time c clkout = 50pf 12 ns clkout fall time c clkout = 50pf 8 ns gate pull down current v gate = 3v (lt3581e, lt3581i) v gate = 3v (lt3581h) v gate = 80v (lt3581e, lt3581i, lt3581h) l l l 800 700 800 933 900 933 1100 1100 1100 a a a ga te leakage current v gate = 50v, gate off 0.01 1 a fault output voltage low 50a into fault pin (lt3581e, lt3581i) 50a into fault pin (lt3581h) l l 100 100 300 400 mv mv f aul t leakage current v fault = 40v, fault off 0.01 1 a fault input voltage low l 700 750 800 mv fault input voltage high l 950 1000 1050 mv guaranteed over the full C40c to 150c operating junction temperature range. operating lifetime is derated at junction temperatures greater than 125c. note 3: current limit guaranteed by design and/or correlation to static test. note 4: this ic includes overtemperature protection that is intended to protect the device during momentary overload conditions. junction temperature will exceed 150c when overtemperature protection is active. continuous operation over the specified maximum operating junction temperature may impair device reliability. lt3581 3581fb
5 for more information www.linear.com/lt3581 typical performance characteristics switch fault current limit vs temperature positive feedback voltage vs temperature clkout duty cycle vs temperature oscillator frequency frequency foldback gate current vs gate voltage switch fault current limit vs duty cycle switch saturation voltage with sw1 and sw2 tied together current sharing between sw1 and sw2 when tied together t a = 25c, unless otherwise noted. duty cycle (%) 20 0 sw1 + sw2 fault current limit (a) 1 2 3 4 30 50 70 80 3581 g01 5 6 40 60 sw1 + sw2 current (a) 0 saturation voltage (mv) 200 250 300 5 4 3581 g02 150 100 0 321 50 450 400 350 sw1 + sw2 current (a) 0 current sharing = sw2/sw1 (%) 50 60 70 5 4 3581 g03 40 30 0 321 10 20 100 90 80 temperature (c) ?50 ?25 0 sw1 + sw2 fault current limit (a) 1 2 3 4 0 50 125 150 3581 g04 5 6 25 75 100 ?50 ?25 0 50 125 150 25 75 100 temperature (c) 1.2100 positive fb voltage (v) 1.2125 1.2200 3581 g05 1.2175 1.2150 temperature (c) ?75 ?50 ?25 10 clkout dc (%) 20 30 40 50 0 50 125 150 3581 g06 60 80 70 25 75 100 ?50 ?25 0 50 125 150 25 75 100 temperature (c) 0 frequency (khz) 3200 3581 g07 2800 2400 2000 1600 1200 800 400 r t = 34k r t = 432k fb voltage (v) 0 0 switching frequency ratio (f sw /f osc ) 1/4 1/5 1/6 1/2 1/3 1 0.2 0.4 0.6 0.8 3581 g08 1.0 1.2 boosting configurations inverting configurations 0 60 80 20 40 gate voltage (v) 0 gate current (a) 1000 3581 g09 900 800 700 600 500 400 200 100 300 125c ?40c 25c lt3581 3581fb
6 for more information www.linear.com/lt3581 typical performance characteristics shdn pin current shdn pin current internal uvlo clkout rise time at 1mhz v in ovlo fault input voltage threshold with hysteresis gate current vs ss voltage commanded current limit vs ss voltage shdn voltage threshold with hysteresis ss voltage (v) 0 0 gate current (a) 100 300 500 700 200 400 600 800 0.25 0.50 0.75 1.00 3581 g10 1.25 1.50 900 1000 ss voltage (v) 0 0 sw1 + sw2 current (a) 1 2 3 0.2 0.4 0.6 0.8 3580 g11 1.0 1.2 4 5 ?50 ?25 0 50 125 150 25 75 100 temperature (c) 1.20 shdn voltage (v) 1.22 1.26 1.28 1.30 1.40 1.34 3581 g12 1.24 1.36 1.38 1.32 shdn rising shdn falling shdn voltage (v) 0 0 shdn pin current (a) 4 8 12 16 20 24 28 32 0.4 1.0 1.4 0.2 1.2 0.6 1.6 0.8 1.8 2.0 3581 g13 125c ?40c 25c shdn voltage (v) 0 shdn pin current (a) 200 250 15 25 3581 g14 150 100 5 10 20 40 3530 50 0 125c ?40c 25c ?50 ?25 0 50 125 150 25 75 100 temperature (c) 2.20 v in voltage (v) 2.22 2.26 2.28 2.30 2.40 2.34 3581 g15 2.24 2.36 2.38 2.32 ?50 ?25 0 50 125 150 25 75 100 temperature (c) 16 v in voltage (v) 18 20 30 24 3581 g17 26 28 22 ?50 ?25 0 50 125 150 25 75 100 temperature (c) 0 fault voltage (v) 1.25 0.50 3581 g18 0.75 1.00 0.25 fault rising fault falling 0 50 250 200 150 100 clkout capacitive load (pf) 0 clkout rise or fall time (ns) 5 15 20 25 50 35 3581 g16 10 40 45 30 clkout fall time clkout rise time t a = 25c, unless otherwise noted. lt3581 3581fb
7 for more information www.linear.com/lt3581 pin functions fb (pin 1/pin 1): positive and negative feedback pin. for a boost or inverting converter, tie a resistor from the fb pin to v out according to the following equations: r fb = v out ? 1.215v 83.3 ? 10 ?6 ? ? ? ? ? ? ; boost or sepic converter r fb = | v out | + 9mv 83.3 ? 10 ?6 ? ? ? ? ? ? ;inverting converter v c (pin 2/pin 2): error amplifier output pin. tie external com pensation network to this pin. gate (pin 3/pin 3): pmos gate drive pin. the gate pin is a pull-down current source, used to drive the gate of an external pmos for output short circuit protection or output disconnect. the gate pin current increases linearly with the ss pins voltage, with a maximum pull-down current of 933a at ss voltages exceeding 500mv. note that if the ss voltage is greater than 500mv and the gate pin voltage is less than 2v, then the gate pin looks like a 2k impedance to ground. see the appendix for more information. fault (pin 4/pin 4): fault indication pin. this active low, bidirectional pin can either be pulled low (below 750mv) by an external source, or internally by the chip to indicate a fault. when pulled low, this pin causes the power switches to turn off, the gate pin to become high impedance, the clkout pin to become disabled, and the ss pin to go through a charge/discharge sequence. the end/absence of a fault is indicated when the voltage on this pin exceeds 1v. a pull-up resistor or current source is needed on this pin to pull it above 1v in the absence of a fault. v in (pin 5/pin 5): input supply pin. must be locally by - passed. sw1 (pins 6, 7/pins 6,7, 8): master switch pin. this is the collector of the internal master npn power switch. minimize the metal trace area connected to this pin to minimize emi. sw2 (pins 8, 9/pins 9, 10, 11): slave switch pin. this is the collector of the internal slave npn power switch. minimize the metal trace area connected to this pin to minimize emi. clkout (pin 10/pin 12): clock output pin. use this pin to synchronize one or more other compatible switching regulator ics to the lt3581. the clock that this pin outputs runs at the same frequency as the internal oscillator of the part or as the sync pin. clkout may also be used as a temperature monitor since the clkout pins duty cycle varies linearly with the parts junction temperature. note that the clkout pin is only meant to drive capacitive loads up to 50pf. shdn (pin 11/pin 13): shutdown pin. in conjunction with the uvlo (undervoltage lockout) circuit, this pin is used to enable/disable the chip and restart the soft-start sequence. drive below 300mv to disable the chip. drive above 1.33v (typical) to activate the chip and restart the soft-start sequence. do not float this pin. rt (pin 12/pin 14): timing resistor pin. adjusts the lt3581s switching frequency. place a resistor from this pin to ground to set the frequency to a fixed free running level. do not float this pin. ss (pin 13/pin 15): soft-start pin. place a soft-start capacitor here. upon start-up, the ss pin will be charged by a (nominally) 250k resistor to about 2.1v. during a fault, the ss pin will be slowly charged up and eventually discharged as part of a timeout sequence (see the state diagram for more information on the ss pins role during a fault event). sync (pin 14/pin 16): to synchronize the switching frequency to an outside clock, simply drive this pin with a clock. the high voltage level of the clock must exceed 1.3v, and the low level must be less than 0.4v. drive this pin to less than 0.4v to revert to the internal free running clock. see the applications information section for more information. gnd (exposed pad pin 15/exposed pad pin 17): ground. exposed pad must be soldered directly to local ground plane. (dfn/msop) lt3581 3581fb
8 for more information www.linear.com/lt3581 block diagram frequency foldback ramp generator comparator driver disable ss ldo v c r gate 14.6k 14.6k sr1 a3 sync clkout n ss shdn c out1 sw1 sw2 fb 27m r s 20m gnd r t rt r c c c v c r fb driver d1 v in sync block uvlo r s q 3581 bd ? + a4 q2 + ? td ~ 30ns vbe 0.9 1.17v 45mv l1 fb adjustable oscillator ? + ? + a1 a3 c ss c in 1.33v + ? ? + + ? 250k 2.1v 1.8v 50mv soft- start startup and fault logic c out2 v out v in m1 gate optional sample mode block r fault fault 933a ? + + ? + ? + ? + ? + ? + ? + ? die temp 22v min 165c v in 750mv sw1 ** **sw overvoltage protection is not guaranteed to protect the lt3581 during sw overvoltage events ** i sw1 42v min 42v min 1.9a min sw2 sample ? + a2 1.215v reference q1 figure 1. block diagram lt3581 3581fb
9 for more information www.linear.com/lt3581 shdn < 1.33v (typical) or v in < 2.3v (typical) shdn > 1.33v (typical) and v in > 2.3v (typical) fault detected ss charges up igate off fault pin pulled low internally by lt3581 switcher disabled clkout disabled ss < 50mv if |v out | drops causing: fb < 1.17v (boost) or fb > 45mv (inverting) fault1 fault1 ss > 1.8v and no fault1 conditions still detected ss < 50mv fault1 fault1 fault1 fault1 fault2 fault pin > 1.0v fault1 = over voltage protection on v in (v in > 22v min) over temperature (t junction > 165c) over current on sw1 (i sw1 > 1.9a min) over voltage protection on sw1 (v sw1 > 42v min) over voltage protection on sw2 (v sw2 > 42v min) fault2 = fault pulled low externally ( fault < 0.75v) chip off all switches disabled i gate off faults cleared initialize ss pulled low normal mode normal operation clkout enabled when ss > 1.8v sample mode q1 & q2 switches forced on every cycle for at least minimum on time i gate fully activated when ss > 500mv soft start i gate enabled ss charges up switcher enabled post fault delay ss slowly discharges local fault over internal fault pin pulldown released by lt3581 ss continues discharging to gnd 3581 sd state diagram figure 2. state diagram lt3581 3581fb
10 for more information www.linear.com/lt3581 operation operation C overview the lt3581 uses a constant-frequency, current mode con - trol scheme to provide excellent line and load regulation. the part s under voltage lockout (uvlo) function, together with soft-start and frequency foldback, offers a controlled means of starting up. fault features are incorporated in the lt3581 to aid in the detection of output shorts, over-volt - age, and overtemperature conditions. refer to the block diagram (figure 1) and the state diagram (figure 2) for the following description of the part s operation. opera tion C start-up several functions are provided to enable a very clean start-up for the lt3581: precise turn-on voltage the shdn pin is compared to an internal voltage reference to give a precise turn on voltage level. taking the shdn pin above 1.33v (typical) enables the part. taking the shdn pin below 300mv shuts down the chip, resulting in extremely low quiescent current. the shdn pin has 30mv of hysteresis to protect against glitches and slow ramping. undervoltage lockout (uvlo) the shdn pin can also be used to create a configurable uvlo. the uvlo function sets the turn on/off of the lt3581 at a desired input voltage (v inuvlo ). figure 3 shows how a resistor divider (or single resistor) from v in to the shdn pin can be used to set v inuvlo . r uvlo2 is optional. it may be left out, in which case set it to infinite in the equation below. for increased accuracy, set r uvlo2 10k. pick r uvlo1 as follows: r uvlo1 = v in uvlo ? 1.33v 1.33v r uvlo2 ? ? ? ? ? ? + 11.6a r uvlo2 (optional) 1.33v r uvlo1 3581 f03 v in v in active/ lockout gnd 11.6a at 1.33v ? + shdn figure 3. configurable uvlo the lt3581 also has internal uvlo circuitry that disables the chip when v in < 2.3v (typical). soft-start of switch current the soft-start circuitry provides for a gradual ramp-up of the switch current (refer to commanded current limit vs ss voltage in typical performance characteristics). when the part is brought out of shutdown, the external ss capacitor is first discharged which resets the states of the logic circuits in the chip. then an integrated 250k resistor pulls the ss pin to ~1.8v. the ramp rate of the ss pin voltage is set by this 250k resistor and the external capacitor connected to this pin. once ss gets to 1.8v, the clkout pin is enabled, and an internal regulator pulls the pin up quickly to ~2.1v. typical values for the external soft-start capacitor range from 100nf to 1f. soft-start of external pmos (if used) the soft-start circuitry also gradually ramps up the gate pin pull-down current which allows an external pmos to slowly turn on (m1 in block diagram). the gate pin current increases linearly with the ss voltage, with a maximum current of 933a when the ss voltage gets above 500mv. note that if the gate pin voltage is less than 2v for ss voltages exceeding 500mv, then the gate pin impedance to ground is 2k. the soft turn on of the external pmos helps limit inrush current at start-up, making hot-plugs of lt3581s feasible and safe. lt3581 3581fb
11 for more information www.linear.com/lt3581 sample mode sample mode is the mechanism used by the lt3581 to aid in the detection of output shorts. it refers to a state of the lt3581 where the master and slave power switches (q1 and q2) are turned on for a minimum period of time every clock cycle (or every few clock cycles in frequency foldback) in order to sample the inductor current. if the sampled current through q1 exceeds the master switch cur - rent limit of 1.9a (min), the lt3581 triggers an overcurrent fault internally (see operation-fault section for details). sample mode is active when fb is out of regulation by more than approximately 3.7% (45mv < fb < 1.17v). frequency foldback the frequency foldback circuit reduces the switching fre - quency when 350mv < fb < 900mv (typical). this feature lowers the minimum duty cycle that the part can achieve, thus allowing better control of the inductor current dur - ing start-up. when the fb voltage is pulled outside of this range, the switching frequency returns to normal. note that the peak inductor current at start-up is a function of many variables including load profile, output capacitance, target v out , v in , switching frequency, etc. test each and every applications performance at start-up to ensure that the peak inductor current does not exceed the minimum fault current limit. operation C regulation the following description of the lt3581s operation as - sumes that the fb voltage is close enough to its regulation target so that the part is not in sample mode. use the block diagram as a reference when stepping through the following description of the lt3581 operating in regulation. at the start of each oscillator cycle, the sr latch (sr1) is set, which turns on the power switches q1 and q2. the collector current through the master switch, q1, is ~1.3 times the collector current through the slave switch, q2, when the collectors of the two switches are tied together. operation q1s emitter current flows through a current sense resistor (r s ) generating a voltage proportional to the total switch current. this voltage (amplified by a4) is added to a sta - bilizing ramp and the resulting sum is fed into the positive terminal of the p wm comparator a3. when the voltage on the positive input of a3 exceeds the voltage on the negative input, the sr latch is reset, turning off the master and slave power switches. the voltage on the negative input of a3 (v c pin) is set by a1 (or a2), which is simply an amplified difference between the fb pin voltage and the reference voltage (1.215v if the lt3581 is configured as a boost converter, or 9mv if configured as an inverting converter). in this manner, the error amplifier sets the correct peak current level to maintain output regulation. as long as the part is not in fault (see operation C fault section) and the ss pin exceeds 1.8v, the lt3581 drives its clkout pin at the frequency set by the rt pin or the sync pin. the clkout pin can be used to synchronize other compatible switching regulator ics (including additional lt3581s) with the lt3581. additionally, clkouts duty cycle varies linearly with the parts junction temperature, and may be used as a temperature monitor. operation C fault the lt3581s fault pin is an active low, bidirectional pin that is pulled low to indicate a fault. each of the following events can trigger a fault in the lt3581: a. f ault1 events: 1. sw overcurrent: a. i sw1 > 1.9a (minimum) b. (i sw1 + i sw2 ) > 3.3a (minimum) 2. v in voltage > 22v (minimum) 3. sw1 voltage and/or sw2 voltage > 42v (minimum) 4. die temperature > 165c b. faul t2 events: 1. pulling the f ault pin low externally lt3581 3581fb
12 for more information www.linear.com/lt3581 operation refer to the state diagram (figure 2) for the following description of the lt3581s operation during a fault event. when a fault is detected, in addition to the fault pin being pulled low internally, the lt3581 also disables its clkout pin, turns off its power switches, and the gate pin becomes high impedance. the external pmos, m1, turns off when the gate of m1 is pulled up to its source by the external r gate resistor (see block diagram). with the external pmos turned off, the power path from v in to v out is cut off, protecting power components downstream. at the same time, a timeout sequence commences where the ss pin is charged up to 1.8v (the ss pin will continue charging up to 2.1v and be held there in the case of a fault1 event that has still not ended), and then discharged to 50mv. this timeout period relieves the part, the pmos, and other downstream power components from electrical figure 4. output short circuit protection of the lt3581 v out 10v/div v clkout 2v/div i l 2a/div v fault 5v/div 3581 f04 5s/div and thermal stress for a minimum amount of time as set by the voltage ramp rate on the ss pin. in the absence of faults, the fault pin is pulled high by the external r fault resistor (typically 100k). figure 4 shows the events that accompany the detection of an output short on the lt3581. lt3581 3581fb
13 for more information www.linear.com/lt3581 applications information figure 5. boost converter C the component values and voltages given are typical values for a 2mhz, 5v to 12v boost boost converter component selection d1 20v, 2a v in 5v r gate 6.04k r fault 100k r fb 130k r t 43.2k c in 4.7f l1 1.5h c c 1nf c out2 4.7f 3581 f05 c ss 0.1f r c 10.5k c out1 4.7f v out 12v i out < 0.83a sw1 sw2 fb clkout gate v c ss v in rt gnd sync fault shdn lt3581 c f 56pf optional pmos the lt3581 can be configured as a boost converter as in figure 5. this topology allows for positive output volt - ages that are higher than the input voltage. an external pmos (optional) driven by the ga te pin of the l t3581 can achieve input or output disconnect during a fault event. a single feedback resistor sets the output voltage. for output voltages higher than 40v, see the charge pump aided regulators section. table 1 is a step-by-step set of equations to calculate component values for the lt3581 when operating as a boost converter. input parameters are input and output voltage, and switching frequency (v in , v out and f osc re- spectively). refer to the appendix for further information on the design equations presented in t able 1. v ariable definitions: v in = input voltage v out = output voltage dc = power switch duty cycle f osc = switching frequency i out = maximum average output current i ripple = inductor ripple current r dson_pmos = r dson of external pmos (set to 0 if not using pmos) table 1. boost design equations parameters/equations step 1: inputs pick v in , v out , and f osc to calculate equations below. step 2: dc dc ? v out ? v in + 0.5v v out + 0.5v ? 0.3v step 3: l1 l typ = v in ? 0.3v ( ) ? dc f osc ? 1a l min = v in ? 0.3v ( ) ? 2 ? dc ? 1 ( ) 2.2a ? f osc ? 1? dc ( ) l max = v in ? 0.3v ( ) ? dc f osc ? 0.35a (1) (2) (3) ? pick l1 out of a range of inductor values where the minimum value of the range is set by l typ or l min , whichever is higher. the maximum value of the range is set by l max . see appendix on how to choose current rating for inductor value chosen. step 4: i ripple i ripple = v in ? 0.3v ( ) ? dc f osc ? l 1 step 5: i out i out = 3.3a ? i ripple 2 ? ? ? ? ? ? ? 1? dc ( ) step 6: d1 v r > v out ; i avg > i out step 7: c out1 , c out2 c out1 = c out2 i out dc f osc 0.01 v out ? 0.50 i out r dson _ pmos ? ? ? ? ? if pmos is not used, then use just one capacitor where c out = c out1 + c out2 . step 8: c in c in c vin + c pwr 3.3a ? dc 45 ? f osc ? 0.005 ? v in + i ripple 8 f osc 0.005 v in ? refer to input capacitor selection in appendix for definition of c vin and c pwr . step 9: r fb r fb = v out ? 1.215v 83.3a step 10: r t r t = 87.6 f osc ?1; f osc in mhz and r t in k ? step 11: pmos only needed for input or output disconnect. see pmos selection in the appendix for information on sizing the pmos, r gate and picking appropriae uvlo components. note 1: the maximum design target for peak switch current is 3.3a and is used in this table. note 2: the final values for c out1 , c out2 and c in may deviate from the above equations in order to obtain desired load transient performance. lt3581 3581fb
14 for more information www.linear.com/lt3581 applications information figure 6. sepic converter C the component values and voltages given are typical values for a 700khz, wide input range (3v to 16v) sepic converter with 5v out sepic converter component selection (coupled or un-coupled inductors) the lt3581 can also be configured as a sepic as shown in figure 6. this topology allows for positive output voltages that are lower, equal, or higher than the input voltage. out - put disconnect is inherently built into the sepic topology, meaning no dc path exists between the input and output due to capacitor c1. this implies that a pmos controlled by the gate pin is not required in the power path. t able 2 is a step-by-step set of equations to calculate component values for the lt3581 when operating as a sepic converter. input parameters are input and output voltage, and switching frequency (v in , v out and f osc re- spectively). refer to the appendix for further information on the design equations presented in t able 2. v ariable definitions: v in = input voltage v out = output voltage dc = power switch duty cycle f osc = switching frequency i out = maximum average output current i ripple = inductor ripple current table 2. sepic design equations parameters/equations step 1: inputs pick v in , v out , and f osc to calculate equations below. step 2: dc d c ? v out + 0.5v v in + v out + 0.5v ? 0.3v step 3: l l typ = v in ? 0.3v ( ) ? dc f osc ? 1a l min = v in ? 0.3v ( ) ? 2 ? dc ? 1 ( ) 2.2a ? f osc ? 1? dc ( ) l max = v in ? 0.3v ( ) ? dc f osc ? 0.35a (1) (2) (3) ? pick l out of a range of inductor values where the minimum value of the range is set by l typ or l min , whichever is higher. the maximum value of the range is set by l max . see appendix on how to choose current rating for inductor value chosen. ? pick l1 = l2 = l for coupled inductors. ? pick l1??l2 = l for un-coupled inductors. step 4: i ripple i ripple = v in ? 0.3v ( ) ? dc f osc ? l ? l = l1 = l2 for coupled inductors. ? l = l1??l2 for un-coupled inductors. step 5: i out i out = 3.3a ? i ripple 2 ? ? ? ? ? ? ? 1? dc ( ) step 6: d1 v r > v in + v out ; i avg > i out step 7: c1 c1 1f; v rating v in step 8: c out c out i out ? dc f osc ? 0.005 ? v out step 9: c in c in c vin + c pwr 3.3a ? dc 45 ? f osc ? 0.005 ? v in + i ripple 8 f osc 0.005 v in ? refer to input capacitor selection in appendix for definition of c vin and c pwr . step 10: r fb r fb = v out ? 1.215v 83.3a step 11: r t r t = 87.6 f osc ? 1; f osc in mhz and r t in k ? note 1: the maximum design target for peak switch current is 3.3a and is used in this table. note 2: the final values for c out , c in and c1 may deviate from the above equations in order to obtain desired load transient performance. d1 30v, 2a v in 3v to 16v r fault 100k r t 124k l1 3.3h 3581 f06 c ss 1f c out 22f 2 l2 3.3h c in 22f v out 5v i out < 0.9a (v in = 3v) i out < 1.5a (v in = 12v) sw1 sw2 fb clkout gate v c ss v in rt gnd sync fault shdn enable lt3581 c f 100pf c1 1f r fb 45.3k c c 2.2nf r c 7.87k lt3581 3581fb
15 for more information www.linear.com/lt3581 due to its unique fb pin, the lt3581 can work in a dual inductor inverting configuration as in figure 7. changing the connections of l2 and the schottky diode in the sepic topology results in generating negative output voltages. this solution results in very low output voltage ripple due to inductor l2 being in series with the output. output disconnect is inherently built into this topology due to the capacitor c1. table 3 is a step-by-step set of equations to calculate component values for the lt3581 when operating as a dual inductor inverting converter. input parameters are input and output voltage, and switching frequency (v in , v out and f osc respectively). refer to the appendix for further information on the design equations presented in table 3. variable definitions: v in = input voltage v out = output voltage dc = power switch duty cycle f osc = switching frequency i out = maximum average output current i ripple = inductor ripple current applications information figure 7. dual inductor inverting converter C the component values and voltages given are typical values for a 2mhz, 5v to C12v inverting topology using coupled inductors dual inductor inverting converter component selection (coupled or un-coupled inductors) table 3. dual inductor inverting design equations parameters/equations step 1: inputs pick v in , v out , and f osc to calculate equations below. step 2: dc d c ? | v out | + 0.5v v in + | v out | + 0.5v ? 0.3v step 3: l l typ = v in ? 0.3v ( ) ? dc f osc ? 1a l min = v in ? 0.3v ( ) ? 2 ? dc ? 1 ( ) 2.2a ? f osc ? 1? dc ( ) l max = v in ? 0.3v ( ) ? dc f osc ? 0.35a (1) (2) (3) ? pick l out of a range of inductor values where the minimum value of the range is set by l typ or l min , whichever is higher. the maximum value of the range is set by l max . see appendix on how to choose current rating for inductor value chosen. ? pick l1 = l2 = l for coupled inductors. ? pick l1??l2 = l for un-coupled inductors. step 4: i ripple i ripple = v in ? 0.3v ( ) ? dc f osc ? l ? l = l1 = l2 for coupled inductors. ? l = l1??l2 for un-coupled inductors. step 5: i out i out = 3.3a ? i ripple 2 ? ? ? ? ? ? ? 1? dc ( ) step 6: d1 v r > v in + | v out | ; i avg > i out step 7: c1 c1 1f; v rating v in + | v out | step 8: c out c out i ripple 8 ? f osc 0.005 ? | v out | ( ) step 9: c in c in c vin + c pwr 3.3a ? dc 45 ? f osc ? 0.005 ? v in + i ripple 8 f osc 0.005 v in ? refer to input capacitor selection in appendix for definition of c vin and c pwr . step 10: r fb r fb = | v out | + 5mv 83.3a step 11: r t r t = 87.6 f osc ? 1; f osc in mhz and r t in k ? note 1: the maximum design target for peak switch current is 3.3a and is used in this table. note 2: the final values for c out , c in and c1 may deviate from the above equations in order to obtain desired load transient performance. l2 3.3h d1 20v 1a v in 5v r fault 100k r t 43.2k l1 3.3h 3581 f07 c ss 100nf c out 4.7f c in 3.3f v out ?12v i out < 625ma sw1 sw2 fb clkout gate v c ss v in rt gnd sync fault shdn enable lt3581 c f 47pf r fb 143k c c 1nf r c 11k c1 1f lt3581 3581fb
16 for more information www.linear.com/lt3581 3581 f08 v out c in b a sync gnd a: return c in ground directly to lt3581 exposed pad pin 17. it is advised to not combine c in ground with gnd except at the exposed pad. b: return c out and c out1 ground directly to lt3581 exposed pad pin 17. it is advised to not combine c out and c out1 ground with gnd except at the exposed pad. shdn clkout + ? v in + ? l1 17 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 c out1 r gate c out d1 m1 d2 applications information layout guidelines for boost, sepic, and dual inductor inverting topologies general layout guidelines ? to optimize thermal per formance, solder the exposed ground pad of the lt3581 to the ground plane, with multiple vias around the pad connecting to additional ground planes. ? a ground plane should be used under the switcher circuitr y to prevent interplane coupling and overall noise. ? high speed switching path (see specific topology for more information) must be kept as short as possible. ? the v c , fb, and rt components should be placed as close to the lt3581 as possible, while being as far away as practically possible from the switch node. the ground for these components should be separated from the switch current path. ? place the bypass capacitor for the v in pin as close as possible to the lt3581. ? place the bypass capacitor for the inductor as close as possible to the inductor. ? the load should connect directly to the positive and negative terminals of the output capacitor for best load regulation. boost topology specific layout guidelines ? keep length of loop (high speed switching path) gov - erning switch, diode d1, output capacitor c out1 , and ground return as short as possible to minimize parasitic inductive spikes at the switch node during switching. sepic topology specific layout guidelines ? keep length of loop (high speed switching path) gov - erning switch, flying capacitor c1, diode d1, output capacitor c out , and ground return as short as possible to minimize parasitic inductive spikes at the switch node during switching. inverting topology specific layout guidelines ? keep ground return path from the cathode of d1 (to chip) separated from output capacitor c out s ground return path (to chip) in order to minimize switching noise coupling into the output. ? keep length of loop (high speed switching path) govern- ing switch, flying capacitor c1, diode d1, and ground return as short as possible to minimize parasitic induc - tive spikes at the switch node during switching. figure 8. suggested component placement for boost topology (msop shown, dfn similar, not to scale.) pin 15 on dfn or pin 17 on msop is the exposed pad which must be soldered directly to the local ground plane for adequate thermal performance. multiple vias to additional ground planes will improve thermal performance figure 9. suggested component placement for sepic topology (msop shown, dfn similar, not to scale.) pin 15 on dfn or pin 17 on msop is the exposed pad which must be soldered directly to the local ground plane for adequate thermal performance. multiple vias to additional ground planes will improve thermal performance 3581 f09 v out c in c1 d1 b a sync gnd a: return c in and l2 ground directly to lt3581 exposed pad pin 17. it is advised to not combine c in and l2 ground with gnd except at the exposed pad. b: return c out grounds directly to lt3581 exposed pad pin 17. it is advised to not combine c out ground with gnd except at the exposed pad. l1, l2: most coupled inductor manufacturers use cross pinout for improved performance. c out shdn clkout + ? v in + ? l2 l1 17 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 lt3581 3581fb
17 for more information www.linear.com/lt3581 applications information thermal considerations overview for the lt3581 to deliver its full output power, it is imp - erative that a good thermal path be provided to dissipate the heat generated within the package. this can be accomplished by taking advantage of the thermal pad on the underside of the ic. it is recommended that multiple vias in the printed cir cuit board be used to conduct heat away from the ic and into a copper plane with as much area as possible. power and thermal calculations power dissipation in the l t3581 chip comes from four primary sources: switch i 2 r losses, switch dynamic losses, npn base drive dc losses, and miscellaneous input current losses. these formulas assume continuous mode operation, so they should not be used for calculating thermal losses or efficiency in discontinuous mode or at light load currents. the following example calculates the power dissipa - tion in the lt3581 for a particular boost application (v in = 5v, v out = 12v, i out = 0.83a, f osc = 2mhz, v d = 0.45v, v cesat = 0.21v). to calculate die junction temperature, use the appropriate thermal resistance number and add in worst-case ambient temperature: t j = t a + ja ? p total table 4. power calculations example for boost converter with v in = 5v, v out = 12v, i out = 0.83a, f osc = 2mhz, v d = 0.45v, v cesat = 0.21v definition of variables equations design example value dc = switch duty cycle d c = v out ? v in + v d v out + v d ? v cesat dc = 12v ? 5v + 0.45v 12v + 0.45v ? 0.21v dc = 60.9% i in = average switch current = power conversion efficiency (typically 88% at high currents) i in = v out ? i out v in ? i in = 12v ? 0.83a 5v ? 0.88 i in = 2.3a p swdc = switch i 2 r loss (dc) r sw = switch resistance (typically 90m combined sw1 and sw2) p swdc = dc ? i in 2 ? r sw p swdc = 0.609 ? (2.3a) 2 ? 90m ? p swdc = 290mw p swac = switch dynamic loss (ac) p swac = 13ns ? i in ? v out ? f osc p swac = 13ns ( ) ? 2.3a ? 12v ? 2mhz ( ) p swac = 718mw p bdc = base drive loss (dc) p bdc = v in ? i in ? dc 45 p bdc = 5v ? 2.3a ? 0.609 45 p bdc = 156mw p inp = input power loss p inp = 9ma ? v in p inp = 9ma ? 5v p inp = 45mw p total = 1.209w figure 10. suggested component placement for dual inductor inverting topology (msop shown, dfn similar, not to scale.) pin 15 on dfn or pin 17 on msop is the exposed pad which must be soldered directly to the local ground plane for adequate thermal performance. multiple vias to additional ground planes will improve thermal performance 3581 f10 c in b a c sync gnd a: return c in ground directly to lt3581 exposed pad pin 17. it is advised to not combine c in ground with gnd except at the exposed pad. b: return c out ground directly to lt3581 exposed pad pin 17. it is advised to not combine c out ground with gnd except at the exposed pad. c: return d1 ground directly to lt3581 exposed pad pin 17. it is advised to not combine d1 ground with gnd except at the exposed pad. l1, l2: most coupled inductor manufacturers use cross pinout for improved performance. c out shdn clkout ? v out gnd v in + ? l2 l1 17 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 c1 d1 lt3581 3581fb
18 for more information www.linear.com/lt3581 applications information where t j = die junction temperature, t a = ambient tem - perature, p total is the final result from the calculations shown in table 4, and ja is the thermal resistance from the silicon junction to the ambient air. the published (http://www.linear.com/designtools/pack - aging/linear_technology_thermal_resistance_table. pdf) ja value is 43c/w for the 4mm 3mm 14-pin dfn package and 45c/w for the 16-lead msop package. in practice, lower ja values are realizable if board layout is performed with appropriate grounding (accounting for heat sinking properties of the board) and other considerations listed in the layout guidelines section. for instance, a ja value of ~24c/w was consistently achieved for both mse and dfn packages of the lt3581 (at v in = 5v, v out = 12v, i out = 0.83a, f osc = 2mhz) when board layout was optimized as per the suggestions in the board layout guidelines section. junction temperature measurement the duty cycle of the clkout signal is linearly propor - tional to die junction temperature, t j . to get a temperature reading, measure the duty cycle of the clkout signal and use the following equation to approximate the junction temperature: t j = dc clkout ? 35% 0.3% where dc clkout is the clkout duty cycle in % and t j is the die junction temperature in c. although the actual die temperature can deviate from the above equation by 15c, the relationship between change in clkout duty cycle and change in die temperature is well defined. basi - cally a 1% change in clkout duty cycle corresponds to a 3.33c change in die temperature. note that the clkout pin is only meant to drive capacitive loads up to 50pf. thermal lockout a fault condition occurs when the die temperature exceeds 165c (see operation section), and the part goes into thermal lockout. the fault condition ceases when the die temperature drops by ~5c (nominal). switching frequency there are several considerations in selecting the operat - ing frequency of the converter. the first is staying clear of sensitive frequency bands, which cannot tolerate any spectral noise. for example, in products incorporating rf communications, the 455khz if frequency is sensitive to any noise, therefore switching above 600khz is desired. some communications have sensitivity to 1.1mhz and in that case a 1.5mhz switching converter frequency may be employed. the second consideration is the physical size of the converter. as the operating frequency goes up, the inductor and filter capacitors go down in value and size. the tradeoff is efficiency, since the losses due to switch - ing dynamics (see thermal considerations), schottky diode charge, and other capacitive loss terms increase proportionally with frequency . oscillator t iming resistor (r t ) the operating frequency of the lt3581 can be set by the internal free-running oscillator. when the sync pin is driven low (< 0.4v), the frequency of operation is set by a resistor from the r t pin to ground. an internally trimmed timing capacitor resides inside the ic. the oscillator frequency is calculated using the following formula: f osc = 87.6 r t + 1 where f osc is in mhz and r t is in k. conversely, r t (in k) can be calculated from the desired frequency (in mhz) using: r t = 87.6 f osc ? 1 lt3581 3581fb
19 for more information www.linear.com/lt3581 enable 1.5h 1.5h 6.8f 4.7f 4.7f 2.2f 100pf sw1 sw2 gate fb v c ss gnd sync clkout v in rt shdn fault lt3581 slave sw1 sw2 gate clkout v c ss gnd sync fb v in rt fault shdn lt3581 master 143k v out ?12v 450ma v in 5v v out 12v 830ma 10k 10.5k 2.2nf 0.1f 0.1f 130k 43.2k 56pf 1nf 43.2k 100k 10k 3581 f11 6.8f figure 11. a single inductor inverting topology is synchronized with a boost regulator to generate C12v and 12v outputs. the external pmos helps disconnect the input from the power paths during fault events also, the fault pins can be tied together so that a fault condition from one lt3581 causes all of the lt3581s to enter fault, until the fault condition disappears. charge pump aided regulators designing charge pumps with the lt3581 can offer ef - ficient solutions with fewer components than traditional cir cuits because of the master/slave switch configuration on the ic. although the slave switch, sw2, operates in phase with the master switch, sw1, it is only the current through the master switch (sw1) that is sensed by the current comparator (a4 in block diagram) as part of the current feedback loop. this method of operation by the master/slave switches can offer the following benefits to charge pump designs: applications information clock synchronization the operating frequency of the lt3581 can be set by an external source by simply providing a digital clock signal into the sync pin (r t resistor still required). the lt3581 will revert to its internal free-running oscillator clock (set by the r t resistor) when the sync pin is driven below 0.4v for a few free-running clock periods. driving sync high for an extended period of time effec - tively stops the operating clock and prevents latch sr1 from becoming set (see block diagram). as a result, the switching operation of the lt3581 will stop and the clkout pin will be held at ground. the duty cycle of the sync signal must be between 20% and 80% for proper operation. also, the frequency of the sync signal must meet the following two criteria: (1) sync may not toggle outside the frequency range of 200khz to 2.5mhz unless it is stopped low (below 0.4v) to enable the free-running oscillator. (2) the sync frequency can always be higher than the free-running oscillator frequency (as set by the r t resistor), f osc , but should not be less than 25% below f osc . clock synchronization of additional regulators the clkout pin of the lt3581 can be used to synchronize one or more other compatible switching regulator ics as shown in figure 11. the frequency of the master lt3581 is set by the external r t resistor. the sync pin of the slave lt3581 is driven by the clkout pin of the master lt3581. note that the rt pin of the slave lt3581 must have a resistor tied to ground. it takes a few clock cycles for the clkout signal to begin oscillating, and its preferable for all lt3581s to have the same internal free-running frequency. therefore, in general, use the same value r t resistor for all of the synchronized lt3581s. lt3581 3581fb
20 for more information www.linear.com/lt3581 applications information ? the slave switch, by not performing a current sense operation like the master switch, can sustain fairly large current spikes when the flying capacitors charge up. since this current spike flows through sw2, it does not affect the operation of the current comparator (a4 in block diagram). ? the master switch, immune from the capacitor current spike (seen only by the slave switch) can sense the inductor current more accurately. ? since the slave switch can sustain large current spikes, the diodes that feed current into the flying capacitors do not need current limiting resistors, leading to efficiency and thermal improvements. high v out charge pump topology the lt3581 can be used in a charge-pump topology as shown in figure 12, multiplying the output of an inductive boost converter. the master switch (sw1) can be used to drive the inductive boost converter (first stage of charge pump), while the slave switch (sw2) can be used to drive one or more other charge pump stages. this topology is useful for high voltage applications including vfd bias supplies. single inductor inverting topology if there is a need to use just one inductor to generate a negative output voltage whose magnitude is greater than v in , the single inductor inverting topology (shown in figure 13) can be used. since the master and slave switches are isolated by a schottky diode, the current spike through c1 will flow only through the slave switch, thereby preventing the current comparator, (a4 in the block diagram), from falsely tripping. output disconnect is inherently built into the single inductor topology. v in 12v v out2 97v 140ma v out1 65v 70ma 24k 2.2f 10h 2.2f 2.2f 0.47f 43.2k 100pf 1nf 100k 2.2f 370k sw1 sw2 fb v c ss gnd sync gate clkout v in rt fault shdn lt3581 3581 f12 8.06k 2.2f 2.2f 2.2f figure 12. high v out charge pump topology can be used to build vfd bias supplies enable c vc2 v in c out v out < 0v and |v out | > |v in | sw1 sw2 gate fb v c ss gnd sync clkout v in rt fault shdn lt3581 100k l1 d1 d2 d3 c1 r fb c vc1 c ss c in r vc r t 3579 f13 figure 13. single inductor inverting topology lt3581 3581fb
21 for more information www.linear.com/lt3581 v out 10v/div ss 1v/div i l 5a/div v in 5v/div 3581 f14 1s/div applications information figure 14. inrush current is well controlled in spite of hot- plugging the re-configured boost converter in figure 18 hot-plug the high inrush current associated with hot-plugging v in can be largely rejected with the use of an external pmos. a simple hot-plug controller can be designed by connecting an external pmos in series with v in , with the gate of the pmos being driven by the gate pin of the lt3581. since the gate pin pull-down current is linearly proportional to the ss voltage, and the ss charge up time is relatively slow, the gate pin pull-down current will increase gradually, thereby turning on the external pmos slowly. controlled in this manner, the pmos acts as an input current limiter when v in hot-plugs or ramps up sharply. likewise, when the pmos is connected in series with the output, inrush currents into the output capacitor can be limited during a hot-plug event. to illustrate this, the circuit in figure 18 was re-configured by adding a large 1500f capacitor to the output. an 18 resistive load was used and a 2.2f capacitor was placed on ss. figure 14 shows the results of hot-plugging this re-configured circuit. notice how the inductor current is well behaved. lt3581 3581fb
22 for more information www.linear.com/lt3581 appendix setting the output voltage the output voltage is set by connecting a resistor (r fb ) from v out to the fb pin. r fb is determined by using the following equation: r fb = | v out ? v fb | 83.3a where v fb is 1.215v (typical) for non-inverting topologies (i.e. boost and sepic regulators) and 5mv (typical) for inverting topologies. power switch duty cycle in order to maintain loop stability and deliver adequate current to the load, the power npns (q1 and q2 in the block diagram) cannot remain on for 100% of each clock cycle. the maximum allowable duty cycle is given by: dc max = t p ?minofftime ( ) t p ? 100% where t p is the clock period and minofftime (found in the electrical characteristics) is typically 60ns. conversely, the power npns (q1 and q2 in the block dia - gram) cannot remain off for 100% of each clock cycle, and will turn on for a minimum on time (minontime) when in regulation. this minontime governs the minimum al - lowable duty cycle given by: dc min = minontime ( ) t p ? 100% where t p is the clock period and minontime (found in the electrical characteristics) is typically 100ns. the application should be designed such that the operating duty cycle is between dc min and dc max . duty cycle equations for several common topologies are given below where v d is the diode forward voltage drop and v cesat is the collector to emitter saturation voltage of the switch. v cesat , with sw1 and sw2 tied together, is typically 250mv when the combined switch current (i sw1 + i sw2 ) is 2.75a. for the boost topology (see figure 5): dc boost ? v out ? v in + v d v out + v d ? v cesat for the sepic or dual inductor inverting topology (see figures 6 and 7): dc sepic _&_invert ? v d + | v out | v in + | v out | + v d ? v cesat for the single inductor inverting topology (see figure 13): dc si_invert = | v out | ? v in + v cesat + 3 ? v d | v out | + 3 ? v d the lt3581 can be used in configurations where the duty cycle is higher than dc max , but it must be operated in the discontinuous conduction mode so that the effective duty cycle is reduced. inductor selection general guidelines: the high frequency operation of the lt3581 allows for the use of small surface mount inductors. for high efficiency, choose inductors with high frequency core material, such as ferrite, to reduce core losses. also to improve efficiency, choose inductors with more volume for a given inductance. the inductor should have low dcr (copper-wire resistance) to reduce i 2 r losses, and must be able to handle the peak inductor current without saturating. note that in some applications, the current handling requirements of the inductor can be lower, such as in the sepic topology where each inductor only carries one half of the total switch current. molded chokes or chip inductors usually do not have enough core area to support peak inductor currents in the 2a to 6a range. to minimize radiated noise, use a toroidal or shielded inductor. see table 5 for a list of inductor manufacturers. table 5. inductor manufacturers sumida cdr6d28mn and cdr7d28mn series www.sumida.com coilcraft msd7342 series www.coilcraft.com vishay ihlp-1616bz-01, ihlp-2020bz-01 and ihlp-2525cz-01 series www.vishay.com taiyo yuden nr series www.t-yuden.com wurth we-pd series www.we-online.com tdk vlf, slf and rlf series www.tdk.com lt3581 3581fb
23 for more information www.linear.com/lt3581 minimum inductance although there can be a tradeoff with efficiency, it is often desirable to minimize board space by choosing smaller inductors. when choosing an inductor, there are three conditions that limit the minimum inductance: (1) provid - ing adequate load current, (2) avoidance of subharmonic oscillations and (3) supplying a minimum ripple current to avoid false tripping of the current comparator . adequate load current small value inductors result in increased ripple currents and thus, due to the limited peak switch current, decrease the average current that can be provided to the load. in order to provide adequate load current, l should be at least: l boost > dc ? v in ? v cesat ( ) 2 ? f osc ? i pk ? | v out | ? i out v in ? ? ? ? ? ? ? or l dual > dc ? v in ? v cesat ( ) 2 ? f osc ? i pk ? | v out | ? i out v in ? ? i out ? ? ? ? ? ? boost topology sepic or inverting topologies where: l boost = l 1 for boost topologies (see figure 5) l dual = l 1 = l 2 for coupled dual inductor topologies (see figures 6 and 7) l dual = l 1 || l 2 for uncoupled dual inductor topologies (see figures 6 and 7) dc = switch duty cycle (see power switch duty cycle section in appendix) i pk = maximum peak switch current; should not exceed 3.3a for a combined sw1 + sw2 current, or 1.9a of sw1 current if sw1 is being used by itself. = power conversion efficiency (typically 88% for boost and 75% for dual inductor topologies at high currents) f osc = switching frequency i out = maximum output current appendix negative values of l boost or l dual indicate that the out- put load current, i out , exceeds the switch current limit capability of the lt3581. avoiding sub-harmonic oscillations the lt3581s internal slope compensation circuit will prevent sub-harmonic oscillations that can occur when the duty cycle is greater than 50%, provided that the inductance exceeds a certain minimum value. in applica - tions that operate with duty cycles greater than 50%, the inductance must be at least: l min = v in ? v cesat ( ) ? 2 ? dc ? 1 ( ) 2.2a ? f osc ? 1 ? dc ( ) where: l min = l 1 for boost topologies (see figure 5) l min = l 1 = l 2 for coupled dual inductor topologies (see figures 6 and 7) l min = l 1 || l 2 for uncoupled dual inductor topologies (see figures 6 and 7) maximum inductance excessive inductance can reduce ripple current to levels t hat are difficult for the current comparator (a4 in the block diagram) to cleanly discriminate, causing duty cycle jitter and/or poor regulation. the maximum inductance can be calculated by: l max = v in ? v cesat 350ma ? dc f osc where: l max = l 1 for boost topologies (see figure 5) l max = l 1 = l 2 for coupled dual inductor topologies (see figures 6 and 7) l max = l 1 || l 2 for uncoupled dual inductor topologies (see figures 6 and 7) lt3581 3581fb
24 for more information www.linear.com/lt3581 appendix inductor current rating inductors must have a rating greater than their peak operating current, or else they could saturate and hence contribute to losses in efficiency. the maximum inductor current (considering start-up and steady-state conditions) is given by: i l _ peak = i lim + v in ? t min _ prop l where: i l_peak = peak inductor current in l 1 for a boost topology , or the peak of the sum of the inductor currents in l1 and l2 for dual inductor topologies. i lim ** = 3.3a with sw1 and sw2 tied t ogether, or 1.9a with just sw1 (this assumes usage of an inductor whose core material soft-saturates such as powdered iron core). t min_prop = 100ns (propagation delay through the current feedback loop). **if using an inductor whose core material saturates hard (e.g., ferrite), then pick i lim to be 5.4a with sw1 and sw2 tied together, or 3a when just sw1 is used. note that these equations offer conservative results for the required inductor current ratings. the current ratings could be lower for applications with light loads, if the ss capacitor is sized appropriately to limit inductor currents at start-up. diode selection schottky diodes, with their low forward voltage drops and fast switching speeds, are recommended for use with the lt3581. choose a schottky diode with low parasitic capaci - tance to reduce reverse current spikes through the power switch of the l t3581. the central semiconductor corp. cmmsh2-40 diode is a very good choice with a 40v reverse voltage rating and an average forward current of 2a. output capacitor selection low esr (equivalent series resistance) capacitors should be used at the output to minimize the output ripple voltage. multilayer ceramic capacitors are an excellent choice, as they have extremely low esr and are available in very small packages. x5r or x7r dielectrics are preferred, as these materials retain their capacitance over wide voltage and temperature ranges. a 10f to 22f output capacitor is sufficient for most applications, but systems with very low output currents may need only 2.2f to 10f. always use a capacitor with a sufficient voltage rating. many ceramic capacitors, particularly 0805 or 0603 case sizes, have greatly reduced capacitance at the desired output voltage. tantalum polymer or os-con capacitors can be used, but it is likely that these capacitors will occupy more board area than a ceramic, and will have higher esr with greater output ripple. input capacitor selection ceramic capacitors make a good choice for the input decoupling capacitor, and should be placed such that it is in close proximity to the v in of the chip as well as to the inductor connected to the input of the power path. if it is not possible to optimally place a single input capacitor, then use two separate capacitorsuse one at the v in of the chip (see equation for c vin in tables 1, 2 and 3) and one at the input to the power path (see equation for c pwr in tables 1, 2 and 3) a 4.7f to 20f input capacitor is sufficient for most applications. table 6 shows a list of several ceramic capacitor man - ufacturers. consult the manufacturers for detailed infor - mation on their entire selection of ceramic parts. table 6: ceramic capacitor manufacturers avx www.avxcorp.com murata www.murata.com taiyo yuden www.t-yuden.com pmos selection an external pmos, controlled by the lt3581s gate pin, can be used to facilitate input or output disconnect. the gate pin turns on the pmos gradually during start-up (see soft-start of external pmos in the operation section), and turns the pmos off when the lt3581 is in shutdown or in fault. lt3581 3581fb
25 for more information www.linear.com/lt3581 appendix the use of the external pmos, controlled by the gate pin, is particularly beneficial when dealing with unintended output shorts in a boost regulator. in a conventional boost regulator, the inductor, schottky diode, and power switches are susceptible to damage in the event of an output short to ground. using an external pmos in the boost regulators power path (path from v in to v out ) controlled by the gate pin, will serve to disconnect the input from the output when the output has a short to ground, thereby helping save the ic, and the other components in the power path from damage. ensure that both, the diode and the inductor can survive low duty cycle current pulses of 3 to 4 times their steady state levels. the pmos chosen must be capable of handling the maxi - mum input or output current depending on whether the pmos is used at the input (see figure 11) or the output (see figure 18). ensure that the pmos is biased with enough sour ce to gate voltage (v sg ) to enhance the device into the triode mode of operation. the higher the v sg voltage that biases the pmos into triode, the lower the r dson of the pmos, thereby lowering power dissipation in the device during normal operation, as well as improving the efficiency of the application in which the pmos is used. the follow - ing equations show the relationship between r gate (see block diagram) and the desired v sg that the pmos is biased with: v sg = v in r gate r gate + 2k ? if v gate < 2v 933a ? r gate if v gate 2v ? ? ? ? ? ? when using a pmos, it is advisable to configure the specific application for undervoltage lockout (see the operations section). the goal is to have v in get to a certain minimum voltage where the pmos has sufficient headroom to attain a high enough v sg , which prevents it from entering the saturation mode of operation during start-up. figure 18 shows the pmos connected in series with the output to act as an output disconnect during a fault con - dition. the schottky diode from the v in pin to the gate pin is optional and helps turn off the pmos quicker in the event of hard shorts. the resistor divider from v in to the shdn pin sets a uvlo of 4v for this application. connecting the pmos in series with the output offers certain advantages over connecting it in series with the input: ? since the load current is always less than the input current for a boost converter, the current rating of the pmos goes down. ? a pmos in series with the output can be biased with a higher overdrive voltage than a pmos used in series with the input, since v out > v in . this higher overdrive results in a lower r dson rating for the pmos, thereby improving the efficiency of the regulator. in contrast, an input connected pmos works as a simple hot-plug controller (covered in more detail in the hot-plug section). the input connected pmos also functions as an inexpensive means of protecting against multiple output shorts in boost applications that synchronize the lt3581 with other compatible ics (see figure 11). table 7 shows a list of several discrete pmos manufa - cturers. consult the manufacturers for detailed information on their entire selection of pmos devices. table 7. discrete pmos manufacturers vishay www.vishay.com fairchild semiconductor www.fairchildsemi.com compensation C adjustment to compensate the feedback loop of the lt3581, a series resistor-capacitor network in parallel with an optional single capacitor should be connected from the v c pin to gnd. for most applications, choose a series capacitor in the range of 1nf to 10nf with 2.2nf being a good starting value. the optional parallel capacitor should range in value from 47pf to 160pf with 100pf being a good starting value. the compensation resistor, r c , is usually in the range of 5k to 50k with 10k being a good starting value. a good technique to compensate a new application is to use a 100k potentiometer in place of the series resistor r c . with the series and parallel capacitors at 2.2nf and 100pf respectively, adjust the potentiometer while observing the transient response and the optimum value for r c can be lt3581 3581fb
26 for more information www.linear.com/lt3581 v out ac-coupled 500mv/div i l 1a/div 3581 f15a 50s/div v out ac-coupled 500mv/div i l 1a/div 3581 f15b 50s/div appendix found. figures 15a to 15c illustrate this process for the circuit of figure 18 with a load current stepped between 540ma and 800ma. figure 15a shows the transient re - sponse with r c equal to 1k. the phase margin is poor as evidenced by the excessive ringing in the output voltage and inductor current. in figure 15b, the value of r c is increased to 3k, which results in a more damped response. figure 15c shows the results when r c is increased further to 10.5k. the transient response is nicely damped and the compensation procedure is complete. figure 15a. transient response shows excessive ringing figure 15b. transient response is better figure 15c. transient response is well damped v out ac-coupled 500mv/div i l 1a/div 3581 f15c 50s/div compensation C theory like all other current mode switching regulators, the lt3581 needs to be compensated for stable and efficient operation. two feedback loops are used in the lt3581: a fast current loop which does not require compensation, and a slower voltage loop which does. standard bode plot analysis can be used to understand and adjust the voltage feedback loop. as with any feedback loop, identifying the gain and phase contribution of the various elements in the loop is critical. figure 16 shows the key equivalent elements of a boost converter. because of the fast current control loop, the power stage of the ic, inductor and diode have been replaced by a combination of the equivalent transconductance amplifier g mp and the current controlled current source (which converts i vin to v in /v out ? i vin ). g mp acts as a current source where the peak input current, i vin , is proportional to the v c voltage. is the efficiency of the switching regulator and is typically about 80%. note that the maximum output currents of the g mp and g ma stages are finite. the output of the g mp stage is limited by the minimum switch current limit (see electrical specifications) and the output of the g ma stage is nominally limited to about 12a. 1.215v reference i vin v in v out i vin v out c out c pl r esr r l r o v c r c c c c f r1 fb r2 r2 ? + ? + 3581 f16 g mp g ma c c : compensation capacitor c out : output capacitor c pl : phase lead capacitor c f : high frequency filter capacitor g ma : transconductor amplifier inside ic g mp : power stage transconductance amplifier r c : compensation resistor r l : output resistance defined as v out /i load(max) r o : output resistance of g ma r1, r2; feedback resistor divider network r esr : output capacitor esr figure 16. boost converter equivalent model lt3581 3581fb
27 for more information www.linear.com/lt3581 from figure 16, the dc gain, poles and zeros can be calculated as follows: dc gain: (breaking loop at fb pin) a dc = a ol (0) = ? v c ? v fb ? ? i vin ? v c ? ? v out ? i vin ? ? v fb ? v out = g ma ? r o ( ) ? g mp ? ? v in v out ? r l 2 ? ? ? ? ? ? ? 0.5r 2 r 1 + 0.5r 2 output pole: p1 = 2 2 ? ? r l ? c out error amp pole: p2 = 1 2 ? ? r o + r c ? ? ? ? ? c c error amp zero: z1 = 1 2 ? ? r c ? c c esr zero: z2 = 1 2 ? ? r esr ? c out rhp zero: z3 = v in 2 ? r l 2 ? ? v out 2 ? l high frequency pole: p3 > f s 3 phase lead zero: z4 = 1 2 ? ? r1 ? c pl phase lead pole: p4 = 1 2 ? ? r1 ? r2 2 r1 + r2 2 ? c pl error amp filter pole: p5 = 1 2 ? ? r c ? r o r c + r o ? c f , c f < c c 10 the current mode zero (z3) is a right half plane zero which can be an issue in feedback control design, but is manage - able with proper external component selection. appendix using the circuit in figure 18 as an example, table 8 shows the parameters used to generate the bode plot shown in figure 17. table 8. bode plot parameters parameter value units comment r l 14.5 application specific c out 9.4 f application specific r esr 1 m application specific r o 305 k not adjustable c c 1000 pf adjustable c f 56 pf optional/adjustable c pl 0 pf optional/adjustable r c 10.5 k adjustable r1 130 k adjustable r2 14.6 k not adjustable v ref 1.215 v not adjustable v out 12 v application specific v in 5 v application specific g ma 270 mho not adjustable g mp 15.1 mho not adjustable l 1.5 h application specific f osc 2 mhz adjustable from figure 17, the phase is C130 when the gain reaches 0db giving a phase margin of 50. the crossover frequency is 17khz, which is more than three times lower than the frequency of the rhp zero z3 to achieve adequate phase margin. figure 17. bode plot for example boost converter frequency (hz) 10 50 gain (db) phase (deg) 70 90 110 130 100 1k 10k 100k 1m 3851 f17 30 10 ?10 ?30 150 170 ?120 ?80 ?40 ?240 ?280 ?160 ?180 ?360 ?320 ?200 0 phase gain lt3581 3581fb
28 for more information www.linear.com/lt3581 typical applications figure 18. 2mhz, 5v to 12v, 830ma boost converter with output short circuit protection v in 5v v in 6.04k 100k 130k d2 d1 m1 43.2k c1 4.7f l1 1.5h 1nf 3581 f18 0.1f 10.5k c2 4.7f v out 12v 830ma c3 4.7f sw1 sw2 fb clkout gate v c ss v in rt gnd sync c1: 4.7f, 16v, x7r, 1206 c2, c3: 4.7f, 25v, x7r, 1206 d1: diodes inc. pd3s230h-7 d2: vishay mss2p3 l1: sumida cdr6d28mn-ir5 m1: vishay siliconix si7123dn fault shdn lt3581 56pf 18.7k 10k transient response with 430ma to 830ma to 430ma load step v out ac-coupled 1v/div load 0.5a/div i l 1a/div 3581 ta02a 50s/div switching waveforms with 830ma load v out ac-coupled 200mv/div v clkout (bw limit) 2v/div v sw 0.5a/div i l 1a/div 3581 ta02b 500ns/div 2mhz, 5v, 1.1a boost converter operates from an input range of 2.8v to 4.2v d1 v in 2.8v to 4.2v 100k 45.3k 43.2k c1 3.3f l1 0.68h 1.5nf 3581 ta03a 0.1f 6.98k v out 5v 1.1a c2 22f sw1 sw2 fb clkout gate v c ss v in rt gnd sync fault shdn lt3581 68pf c1: 3.3f, 16v, x7r, 1206 c2: 22f, 16v, x7r, 1210 d1: diodes inc. pd3s230h-7 l1: vishay ihlp1616 bz-01-or68 (only 4.1mm 4.5mm 2mm) efficiency and power loss at v in = 3.3v load current (ma) 0 50 efficiency (%) power loss (mw) 55 65 70 75 400 90 3581 ta03b 60 200 1200 1000800600 80 85 0 200 600 2000 1200 1400 1600 1800 400 800 1000 lt3581 3581fb
29 for more information www.linear.com/lt3581 high efficiency, vfd (vacuum fluorescent display) power supply switches at 2mhz to avoid am band typical applications v in 9v to 16v v in v out2 97v 90ma (v in = 9v) 140ma (v in = 12v) 180ma (v in = 16v) v out1 65v 60ma (v in = 9v) 70ma (v in = 12v) 90ma (v in = 16v) 24k c2 2.2f l1 10h c5 2.2f c4 2.2f 0.47f 43.2k 100pf 1nf 100k c1 2.2f 365k d3 d2 d1 d7 d9* 10v d4 d5 d6 10k 32.6k sw1 sw2 fb v c ss gnd sync gate clkout v in rt fault shdn lt3581 3581 ta04a 8.06k c6 2.2f c7 2.2f c3 2.2f d8* m1* c1: 2.2f, 25v, x7r, 1206 c2 to c7: 2.2f, 50v, x7r, 1206 d1 to d7: central semi sod123f d8: central semi cmdsh-3tr d9: central semi cmhz5240b-ltz l1: taiyo yuden nr6045t100m m1: vishay siliconix si7611dn *optional, for output short-circuit protection danger high voltage! operation by high voltage trained personnel only transient response with 60ma to 140ma to 60ma load step on v out2 (v in = 12v) v out ac-coupled 2v/div i load 0.1a/div i l 0.5a/div 3581 ta04b 100s/div start-up waveforms v out2 50v/div v out1 50v/div v ss 1v/div i l 0.5a/div 3581 ta04c 100ms/div efficiency and power loss at v in = 12v total output power (w) 0 70 efficiency (%) power loss (mw) 75 8 90 3581 ta04d 4 201612 80 85 1.0 3.0 1.5 2.0 2.5 lt3581 3581fb
30 for more information www.linear.com/lt3581 typical applications 2mhz, 12v sepic converter can accept input voltages from 9v to 16v v in 9v to 16v 100k 130k 43.2k c1 3.3f 2.2nf 3581 ta06a 0.1f c3 10f 10k v out 12v 1a (v in = 9v) 1.1a (v in = 12v) 1.3a (v in = 16v) c2 2.2f sw1 sw2 fb clkout gate v c ss v in rt gnd sync fault shdn lt3581 100pf c1: 3.3f, 25v, x7r, 1206 c2: 2.2f, 50v, x7r, 1206 c3: 10f, 25v, x7r, 1210 d1: central semi ctlsh2-40m832 l1, l2: coilcraft msd7342-332mlb l2 3.3h l1 3.3h d1 efficiency line regulation with no load load regulation at v in = 12 load current (ma) 0 50 efficiency (%) 55 65 70 75 1200 100 95 3581 ta06b 60 300 1500 900 600 80 85 90 v in = 16v v in = 9v v in = 12v v in (v) 8 11.990 v out (v) 11.998 11.996 11.994 11.992 12.000 9 12 1413 10 15 11 16 17 3581 ta06c line regulation ~0.0044%/v i load (ma) 0 11.96 v out (v) 12.00 11.99 11.98 11.97 12.01 400 800600 1000 200 1200 1400 3581 ta06d load regulation ~0.25%/a lt3581 3581fb
31 for more information www.linear.com/lt3581 typical applications efficiency v bat 3v to 36v (v bat at start-up = 6v to 16v) 100k 10k 24.9k 174k c1 10f 2.2nf 3581 ta07a 1f c5 47f 2 10k v out 3.3v 0.9a (3v < v bat < 9v) 1.5a (v bat = 9v) c2 10nf q1 c3 4.7f c4 2.2f sw1 sw2 fb clkout gate v c ss v in rt gnd sync fault shdn lt3581 47pf c1: 10f, 50v, x7r, 1210 c2: 10nf, 25v, x7r, 0603 c3: 4.7f, 25v, x7r, 1206 c4: 2.2f, 50v, x7r, 1206 c5: 47f, 10v, x7r, 1210 d1: central semi cmhz5248b-ltz d2: central semi cmmsh2-40 d3: diodes inc. pd3s230h-7 l1, l2: coilcraft msd7342-332mlb m1: 2n7002 q1: mmbt3904 l2 3.3h l1 3.3h d2 m1 d3 d1 18v 470pf 10k 200k wide input range, 3.3v sepic converter can operate from 3v to 36v wide input range sepic can ride through v b at voltages that are higher than v in_ovp v bat 10v/div v out 2v/div i l 2a/div 3581 ta07c 1s/div v bat = 17v v bat = 31v v out = 3.3v load current (ma) 0 50 efficiency (%) 55 65 70 75 400 80 3581 ta07b 60 1600 800 1200 v bat = 3v v bat = 9v v bat = 12v lt3581 3581fb
32 for more information www.linear.com/lt3581 typical applications 1mhz, 12v charge pump topology uses only single inductor v in 5v 100k 130k 86.6k c1 3.3f 2.2nf 3581 ta08a 0.1f c4 10f c5 10f 16.9k v out + 12v 0.27a v out ? ?12v 0.27a c2 1f sw1 sw2 fb clkout gate v c ss v in rt gnd sync fault shdn lt3581 100pf c1: 3.3f, 25v, x7r, 1206 c2, c3: 1f, 25v, x7r, 1206 c4, c5: 10f, 50v, x7r, 1210 d1 to d5: diodes inc. pd3s230h-7 l1: vishay ihlp-2525cz-01-8r2 r1: 2.4k, 2w *if driving asymmmetrical loads, place a 2.4k, 2w resistor from the 12v output to the ?12v output for improved load regulation of the ?12v output d2 d1 l1 8.2h d3 c3 1f d4 d5 r1 *2.4k efficiency and power loss with symmetric load 700khz, C5v inverting converter can accept input voltages from 3v to 16v v in 3v to 16v 100k 60.4k 124k c1 22f 2.2nf 3581 ta09a 0.1f c3 22f 6.19k v out ?5v 0.9a (v in = 3.3v) 1.5a (v in = 12v) 1.6a (v in = 16v) c2 1f sw1 sw2 fb clkout gate v c ss v in rt gnd sync fault shdn lt3581 56pf c1: 22f, 25v, x7r, 1210 c2: 1f, 50v, x7r, 1206 c3: 22f, 16v, x7r, 1210 d1: vishay ssb44 l1, l2: coilcraft msd7342-332mlb l2 3.3h d1 l1 3.3h efficiency load current (ma) 0 50 efficiency (%) power loss (mw) 55 65 70 75 150 50 90 3581 ta08b 60 100 300250200 80 85 0 200 600 1800 1200 1400 1600 400 800 1000 load current (ma) 0 50 efficiency (%) 55 65 70 75 300 90 3581 ta09b 60 1800 900 1500 600 1200 80 85 v in = 3.3v v in = 12v v in = 16v efficiency 700khz, 5v sepic can accept input voltages from 3v to 16v v in 3v to 16v 100k 45.3k 124k c1 22f 2.2nf 3581 ta10a 1f c3 22f 2 7.87k v out 5v 0.9a (v in = 3v) 1.5a (12v v in 16v) c2 1f sw1 sw2 fb clkout gate v c ss v in rt gnd sync fault shdn lt3581 100pf c1: 22f, 25v, x7r, 1210 c2: 1f, 50v, x7r, 1206 c3: 22f, 16v, x7r, 1210 d1: diodes inc. b230la l1, l2: coilcraft msd7342-332mlb l2 3.3h l1 3.3h d1 load current (ma) 0 50 efficiency (%) 55 65 70 75 400 90 3581 ta10b 60 1600 800 1200 80 85 v in = 3.3v v in = 12v v in = 16v lt3581 3581fb
33 for more information www.linear.com/lt3581 package description please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings. msop (mse16) 0213 rev f 0.53 0.152 (.021 .006) seating plane 0.18 (.007) 1.10 (.043) max 0.17 ?0.27 (.007 ? .011) typ 0.86 (.034) ref 0.50 (.0197) bsc 16 16151413121110 1 2 3 4 5 6 7 8 9 9 1 8 note: 1. dimensions in millimeter/(inch) 2. drawing not to scale 3. dimension does not include mold flash, protrusions or gate burrs. mold flash, protrusions or gate burrs shall not exceed 0.152mm (.006") per side 4. dimension does not include interlead flash or protrusions. interlead flash or protrusions shall not exceed 0.152mm (.006") per side 5. lead coplanarity (bottom of leads after forming) shall be 0.102mm (.004") max 6. exposed pad dimension does include mold flash. mold flash on e-pad shall not exceed 0.254mm (.010") per side. 0.254 (.010) 0 ? 6 typ detail ?a? detail ?a? gauge plane 5.10 (.201) min 3.20 ? 3.45 (.126 ? .136) 0.889 0.127 (.035 .005) recommended solder pad layout 0.305 0.038 (.0120 .0015) typ 0.50 (.0197) bsc bottom view of exposed pad option 2.845 0.102 (.112 .004) 2.845 0.102 (.112 .004) 4.039 0.102 (.159 .004) (note 3) 1.651 0.102 (.065 .004) 1.651 0.102 (.065 .004) 0.1016 0.0508 (.004 .002) 3.00 0.102 (.118 .004) (note 4) 0.280 0.076 (.011 .003) ref 4.90 0.152 (.193 .006) detail ?b? detail ?b? corner tail is part of the leadframe feature. for reference only no measurement purpose 0.12 ref 0.35 ref mse package 16-lead plastic msop, exposed die pad (reference ltc dwg # 05-08-1667 rev f) lt3581 3581fb
34 for more information www.linear.com/lt3581 de package 14-lead plastic dfn (4mm 3mm) (reference ltc dwg # 05-08-1708 rev b) 3.00 0.10 (2 sides) 4.00 0.10 (2 sides) note: 1. drawing proposed to be made variation of version (wged-3) in jedec package outline mo-229 2. drawing not to scale 3. all dimensions are in millimeters 4. dimensions of exposed pad on bottom of package do not include mold flash. mold flash, if present, shall not exceed 0.15mm on any side 5. exposed pad shall be solder plated 6. shaded area is only a reference for pin 1 location on the top and bottom of package 0.40 0.10 bottom view?exposed pad 1.70 0.10 0.75 0.05 r = 0.115 typ r = 0.05 typ 3.00 ref 1.70 0.05 1 7 14 8 pin 1 top mark (see note 6) 0.200 ref 0.00 ? 0.05 (de14) dfn 0806 rev b pin 1 notch r = 0.20 or 0.35 45 chamfer 3.00 ref recommended solder pad pitch and dimensions apply solder mask to areas that are not soldered 2.20 0.05 0.70 0.05 3.60 0.05 package outline 0.25 0.05 0.25 0.05 0.50 bsc 3.30 0.05 3.30 0.10 0.50 bsc package description please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings. lt3581 3581fb
35 for more information www.linear.com/lt3581 information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no representa - tion that the interconnection of its circuits as described herein will not infringe on existing patent rights. revision history rev date description page number a 11/13 added h-grade to absolute maximum ratings table and order information table clarified electrical characteristics 2 4 b 07/14 clarified fault output voltage low on electrical characteristics table, typ was 150, changed to 100 4 lt3581 3581fb
36 for more information www.linear.com/lt3581 linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 ? linear technology corporation 2010 lt 0714 rev b ? printed in usa (408) 432-1900 fax : (408) 434-0507 www.linear.com/lt3581 related parts part number description comments lt3580 2a (i sw ), 2.5mhz, high efficiency step-up dc/dc converter v in = 2.5v to 32v, v out(max) = 42v, i q = 1ma, i sd < 1a, 3mm 3mm dfn-8, msop-8e packages l t3471 dual output 1.3a (i sw ), 1.2mhz, high efficiency step-up dc/dc converter v in = 2.4v to 16v, v out(max) = 40v, i q = 2.5ma, i sd < 1a, 3mm 3mm dfn-10 package lt3479 40v, 3a, full featured dc/dc converter with soft-start and inrush current protection v in = 2.5v to 24v, v out(max) = 40v, i q = analog/pwm, i sd < 1a, dfn, tssop packages lt3477 40v, 3a, full featured dc/dc converter v in = 2.5v to 25v, v out(max) = 40v, i q = analog/pwm, i sd < 1a, qfn, tssop-20e packages lt1946/lt1946a 1.5a (i sw ), 1.2mhz/2.7mhz, high efficiency step-up dc/dc converter v in = 2.6v to 16v, v out(max) = 34v, i q = 3.2ma, i sd < 1a, ms8e package lt1935 2a (i sw ), 40v, 1.2mhz, high efficiency step-up dc/dc converter v in = 2.3v to 16v, v out(max) = 40v, i q = 3ma, i sd < 1a, thinsot package lt1310 2a (i sw ), 40v, 1.2mhz, high efficiency step-up dc/dc converter v in = 2.3v to 16v, v out(max) = 40v, i q = 3ma, i sd < 1a, thinsot package lt3436 3a (i sw ), 800khz, 34v step-up dc/dc converter v in = 3v to 25v, v out(max) = 34v, i q = 0.9ma, i sd < 6a, tssop-16e package typical application 5v to C12v inverting converter switches at 2mhz v in 5v 100k 143k 43.2k c1 3.3f 1nf 3581 ta05a 0.1f c3 4.7f 11k v out ?12v 625ma c2 1f sw1 sw2 fb clkout gate v c ss v in rt gnd sync fault shdn lt3581 47pf c1: 3.3f, 16v, x7r, 1206 c2: 1f, 25v, x7r, 1206 c3: 4.7f, 25v, x7r, 1206 d1: diodes inc. pd3s230h-7 l1, l2: coilcraft msd7342-332mlb l2 3.3h d1 l1 3.3h efficiency and power loss 50 55 65 70 75 90 60 80 85 load current (ma) 0 efficiency (%) power loss (mw) 250 3581 ta05b 125 625 500 375 0 200 600 2000 1200 1400 1600 1800 400 800 1000 lt3581 3581fb

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